Multi-supply voltage semiconductor chip designs support several frequency and power saving requirements for different applications. Voltage regions can be defined strategically for these designs to help efficiently manage both performance and power distribution criteria while satisfying all other chip floor plan constraints.
Voltage regions on the semiconductor chip are powered independently and their circuit compositions must meet both timing and power distribution goals. Complex multi-power domain regions allow sharing of different circuit domains in the same chip area in order to satisfy these design goals without sacrificing chip area.
Voltage region power distribution networks are usually created by the same algorithmic power router used for the full-chip power grid. Advanced chip power routing methodology supports usage of nested voltage regions in complex chip designs. Examples of such complex designs involve those with overlapping global infrastructure components such as the global clock distribution network, which may require that clock circuitry of a different power domain be placed within a region supporting circuits of a totally different domain. Level-translator regions are another example in which very tiny circuits involving multiple domains (e.g., VDD and VIO) are embedded within a much larger region of the predominant power domain (e.g., VIO). These nested regions are more susceptible to power connection problems than other independent voltage regions. This is because the quality of their power distribution networks depends not only on the quality of the routing specifications defined for these regions, but also on the quality of the parent power distribution networks.
Definitions of voltage regions and their physical power networks not only have to enable effective intermixing of different circuit domains, but also efficient power distribution of applicable domains to all circuits placed within. New multi-supply voltage chip designs, especially those with a large number of circuits placed at the chip-level floor plan, use computer-aided programs to achieve the above voltage region design goals. These chip designs typically depend on usage of conventional full-chip physical design checking processes to validate the full-chip physical power distribution network. These include layout-versus-schematic (LVS) checking, design rule checking (DRC), and power grid analysis used for chip electromigration and IR-drop analysis. Partial checking of just the voltage region networks is not feasible with these methods.
As a chip floor plan evolves over time to support various required design changes, power connection problems may arise for previously defined power regions and circuits placed within them. Unfortunately, such issues typically are not identified until full chip physical design checks are performed. As is the case of the above identified application, Ser. No. 11/055,863, full-chip checking processes are usually performed late in the design phase since they require more complete circuit electrical power and physical layout data. When the full-chip checking jobs finish, additional analysis is typically involved in order to isolate region power distribution network problems from other power-related problems. In design environments where full chip checking capability for multi-voltage chip designs may still be limited, such issues may even go undetected until actual hardware deployment.